Berkeley RISC

Both RISC and MIPS shared a number of design features. Both used a load-store design in which all memory accesses were explicitly handled by instructions that loaded data into or from processor registers, and added a much larger set of them to work with. Older designs, now retroactively known as CISC, tended to make memory access a part of other instructions. In the RISC design the clean separation of functional units within the core logic of the chip makes it much easier to add an instruction pipeline, and thereby dramatically increase performance.

Where the two differed was in their handling of the registers. In RISC the registers were handled automatically to a large degree; although there were a set of 64 registers in total, only eight of them were globally accessible, and another eight locally. The rest were handled by the processor itself to create a stack. The basic idea was to dramatically improve performance of an extremely common programming concept, the procedure call. Procedures are small bits of a program that are tasked with some small part of a larger application, and include their own local working storage. In the RISC design the processor gave each procedure eight registers to work with, thereby speeding processing. When the procedure "returned", those eight registers would be given to some other procedure in turn.

Compared to other designs, the Berkeley system, known as register windows, simplified procedure handling. Almost all computer languages use a system known as a activation record or stack frame that contains the address of who called it, the data that was passed in, and any results that need to be returned. In the vast majority of cases these frames are small, typically with three or less inputs and one or no outputs. In the Berkeley design, then, the entire procedure stack would most likely fit entirely within the register window, dramatically improving performance.