IBM POWER

The architecture

The POWER design is descended directly from the earlier IBM 801 CPU, widely considered to be the first true RISC chip design. It was used in a number of applications inside IBM hardware, but did not become public until they released the poorly-performing IBM PC/RT in the mid-1980s.

At about the same time the PC/RT was being released, IBM started the America Project, to design the most powerful CPU on the market. They were interested primarily in fixing two problems in the 801 design in the resulting POWER design:

1. the 801 required all instructions to complete in one clock cycle, which eliminated floating point instructions
2. although the decoder was pipelined as a side effect of these single-cycle operations, they didn't use superscalar effects

The system used thirty-two 32-bit integer registerss and another thirty-two 64-bit floating point registers, each in their own unit. The branch unit also included a number of "private" registers for its own use, including the program counter.

The 801 was a simple design, and an overcorrection to its simplicity resulted in the POWER design being more complex than most RISC CPUs. For instance, the POWER (and PowerPC) instruction set includes over 100 op-codes of variable length, many of which are variations on others. This compares (for instance) with the ARM which has only 34 instructions.

Another interesting feature of the architecture is a virtual address system which maps all addresses into a 52-bit space. In this way applications can share memory in a "flat" 32-bit space, and all of the programs can have different blocks of 32-bits each.

Implementations

The first POWER1 CPUs consisted of three chips; branch, integer and floating point. These were wired together on a largish motherboard to produce a single system. POWER1 was used primarily in the RS/6000 series of workstations.

POWER2 was a product-improved POWER1 and was the longest-lived of the POWER series, released in 1993 and still used five years later. It added a second floating-point unit, 256k of cache and 128-bit floating point math.

POWER3 followed in 1998, moving to a full 64-bit implementation, while remaining completely compatible with the POWER instruction set. This had been one of the goals of the PowerPC project and the POWER3 was the first of the IBM processors to take advantage of it. It also added a third ALU and a second instruction decoder, for a total of eight functional units.

The POWER4 series places two complete CPU cores (otherwise similar to the POWER3) on a single chip, speeds it up, and adds high-speed connections to up to three other pairs of POWER4 CPUs. They can be placed together on a motherboard to produce an 8-CPU SMP building block. When processing requires high throughput instead of high code complexity, one of a pair of cores can be turned off so that the remaining cores have the entire bus and L3 cache to themselves. The POWER4, even in single form, is considered by many to be the most powerful CPU available. In 2003, IBM introduced a single CPU core version of the POWER4 called the 970. It was employed in the newest generation of Apple desktop computers (i.e., the G5).