SPARC

Implementations of SPARC architecture were initially designed and used for workstations, and then used for larger SMP servers produced by Sun Microsystems and Fujitsu among others.

There have been several revisions of the architecture. Most recent ones are the version 8 and the version 9.

Features

The SPARC architecture was heavily influenced by the earlier designs of the RISC I & II from the University of California, Berkeley. These original RISC designs were minimalist, including as few features or op-codes as possible and demanding that all operations complete in one cycle. This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot.

The SPARC processor usually contains as many as 128 general purpose registers.
At any point, only 32 of them are available - 8 are global registers and the other 24 are from the stack of registers. These 24 registers form what is called a register window, and at function call/return, this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for keeping values across function calls.
The "Scalable" in SPARC comes from the fact that the SPARC specification allows up to 32 windows. So the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement minimum to reduce the context switching time. Other architectures that include similar register windows include Intel i960, IA-64, and AMD 29000.

In version 8, the floating-point register file has 16 double precision registers.
Each of them can be used as two single precision registers,
providing a total of 32 single precision registers.
An odd-even number pair of double precision registers can be used as a quad precision register, thus allowing 8 quad precision registers.
Version 9 added 16 more double precision registers,
but these additional double precision registers can not be used as single precision registers.

Tagged add and subtract instructions perform adds and subtracts on values assuming that the bottom two bits do not participate in the computation. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.

History

The architecture has gone through a few revisions and has gained multiply and divide functionality in version 8. The most substantial upgrade resulted in the version 9 which is a 64-bit SPARC specification.

Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, so as to be used as reference systems for SPEC CPU95 and CPU2000 benchmarks.

External links

• SPARC International, Inc.
• SPARC Standards Documents Depository
• LEON2 An open source SPARC implementation
• ERC32 A SPARC V7 radiation-tolerant CPU
• Solaris Operating System for SPARC Platforms
• UltraSPARC Processors
• FreeBSD 64-bit SPARC Port
• NetBSD 32-bit SPARC Port
• NetBSD 64-bit SPARC Port
• OpenBSD 32-bit SPARC Port
• OpenBSD 64-bit SPARC Port
• UltraLinux - Linux SPARC port (32 and 64 bits)
• SPARC processor images and descriptions at cpu-collection.de
• UltraSPARC Modules