SystemC

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Description

SystemC is a often thought of as a hardware description language like VHDL and Verilog, but is more aptly described as a system description language, since it exhibits its real power at the behaviour level of modelling. SystemC is a set of library routines and macros implemented in C++, which makes it possible to simulate concurrent processes, each described by ordinary C++ syntax. Instantiated in the SystemC framework, the objects described in this manner may communicate in a simulated real-time environment, using signals of all the datatypes offered by C++, some additional ones offered by the SystemC library, as well as user defined.

The behaviours (processes) defined may be instantiated any number of times, and provisions are made for processes defined by hierarchies of other processes, as one would expect.

The language thus offered has semantical similarities to VHDL and Verilog, but may be said to have a syntactical overhead compared to these. On the other hand, greater freedom of expressiveness is offered in return, like object oriented design partitioning, template classes and dynamic memory allocation. Which is more: SystemC is both a description language and a simulation kernel. The code written will compile together with the library's simulation kernel to give an executable that behaves like the described model when it is run. The performance of this simulation kernel is not to be compared with that of commercial VHDL/Verilog simulators at the present.

Language Features

Modules

Modules are the basic building blocks of an SystemC design hierarchy. A SystemC model consists usual of several modules which communicate via ports.

Ports

Ports allow the communication from inside of an module to the outside (usually other modules)

Processes

Processes are the main computation elements. They are concurrent.

Channels

Channels are the communication element of SystemC. They could be either simple wires or complex communication mechanism like fifo's or even bus channels.

Elementary Channels:

signal

buffer

fifo

mutex

semaphore

Interfaces

Ports uses interfaces to communicate with channels

Events

Allow the synchronisation between processes.

Data types

SystemC introduces several data types which support the modeling of hardware.

Extended standard types:

sc_int<> 64-bit signed integer

sc_uint<> 64-bit unsigned integer

sc_bigint<> arbitrary precision signed integer

sc_biguint<> arbitrary precision unsigned integer

Logic types:

sc_bit 2-valued single bit

sc_logic 4-valued single bit

sc_bv<> vector of sc_bit

sc_lv<> vector of sc_logic

Fixed point types:

sc_fixed<> templated signed fixed point

sc_ufixed<> templated unsigned fixed point

sc_fix untemplated signed fixed point

sc_ufix untemplated unsigned fixed point

Example

Example code of an adder:

include "systemc.h" SC_MODULE(adder) // module (class) declaration { sc_in a, b; // ports sc_out sum;

 void do_add() // process
{
sum = a + b;
}
 SC_CTOR(adder) // constructor
{
SC_METHOD(do_add); // register do_add to kernel
sensitive << a << b; // sensitivity list of do_add
}
}

Links

Further information about this open-source project can be found at SystemC homepage.

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